Tuesday, December 27, 2011

Physical Design Engineers RTL to GDSII, 3-8 years exp, Hyderabad / Secunderabad

Xilinx India Technology Services Pvt. Ltd. -   As an Physical Design integration engineer, you will be responsible for full-chip implementation of complex & next generation SoCs. You will execute full-chip timing closure using Static-timing analysis techniques. You will be an expert in Full-chip EM/IR, power and clock routing, sign-off release checks including electrica

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