R&D Engineer, II (DDR, IP Verification), 3-7 years exp, Bengaluru/Bangalore

Synopsys -  The candidate must have: - Full understanding of design using SV, verilog and working experience with Perl and C/C++. - Familiarity with OOP and have coding and debugging experience in SystemVerilog - Exposure to formal verification, assertions/SVA, functional coverage, gate level simulations wit

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